Dual Resampler 1Y

Features

  • General-purpose interpolator
  • Arbitrary (even time-varying and non-integer) input / output sample rate ratios
  • Optimized for 10-bit input and output datapath word widths (others on request)
  • Designed for maximum speed (fMAX > 140 - 300 MHz, depending on device)
  • Ideal for the following applications:
    • Digital modulators/demodulators
    • Wireless & wired telecommunications systems

Block Diagram

Description

The CommStack Dual Resampler 1Y megafunction resamples a complex digital baseband signal, interpolating it from a lower-rate complex input sequence to a higher-rate complex output sequence.

While many interpolators operate only at fixed integer input-to-output sampling rate ratios 1:N, and more complicated multi-rate (interpolate / decimate) schemes are often used just to obtain fixed integer-fractional ratios M:N, the CommStack Resampler megafunction offers much greater flexibility in a smaller footprint. CommStack's design supports not only fixed integer and fixed integer-fractional ratios, but also arbitrary non-fixed ratios Y, where Y may be time varying. This capability can be used to adjust output versus input phase continuously or to change input and/or output sampling rates on the fly, even by non-integer ratios.

The Dual Resampler 1Y function may be used as the final stage of digital modulator designs or as the stage just prior to an upconverter in such applications as DOCSIS, LMDS, or MMDS. The input signal may be in any of a variety of formats, including AM, BPSK, QPSK, GMSK, 8-PSK, OFDM, or 16- to 256-QAM.

The datapath is optimized for 10-bit inputs and outputs, but other datapath word widths may be implemented on a customized basis at nominal cost. Additional precision is implemented internally to maintain 10-bit accuracy in the result.

With performance from 140 Mbps to over 300 Mbps, CommStack's Dual Resampler 1Y megafunction provides a high-speed and flexible interpolator capability well suited to many modern digital signal processing applications.

Device Utilization Examples

CommStack is a partner in the Altera Megafunction Partners Program and has optimized this block for the following Altera CMOS-based PLDs: ACEX™ 1K, FLEX® 10KE, APEX™ 20KE, APEX 20KC, and Mercury™ devices.

Typical Altera Device Utilization
Device Speed Grade Logic Cells Embedded Array Blocks fMAX (typical)
EP1K100, EPF10K100E -1 828 1 147 MHz
EP20K100E -1 827 1 177 MHz
EP20K100C -7 827 1 210 MHz
EP1M120 -5 828 2 308 MHz

 

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